|
|
union { |
|
struct { |
|
uint32_t | axi0_wr_limit_stall: 1 |
| |
|
uint32_t | axi1_ar_stalled: 1 |
| |
|
uint32_t | axi1_rd_limit_stall: 1 |
| |
|
uint32_t | axi1_wr_stalled: 1 |
| |
|
uint32_t | axi1_w_stalled: 1 |
| |
|
uint32_t | axi1_wr_limit_stall: 1 |
| |
|
uint32_t | wgt_idle_c1: 1 |
| |
|
uint32_t | bas_idle_c1: 1 |
| |
|
uint32_t | ib0_ai_valid_c1: 1 |
| |
|
uint32_t | ib0_ai_ready_c1: 1 |
| |
|
uint32_t | ib1_ai_valid_c1: 1 |
| |
|
uint32_t | ib1_ai_ready_c1: 1 |
| |
|
uint32_t | ib0_ao_valid_c1: 1 |
| |
|
uint32_t | ib0_ao_ready_c1: 1 |
| |
|
uint32_t | ib1_ao_valid_c1: 1 |
| |
|
uint32_t | ib1_ao_ready_c1: 1 |
| |
|
uint32_t | ob0_valid_c1: 1 |
| |
|
uint32_t | ob0_ready_c1: 1 |
| |
|
uint32_t | ob1_valid_c1: 1 |
| |
|
uint32_t | ob1_ready_c1: 1 |
| |
|
uint32_t | wd_bitstream_valid_c1: 1 |
| |
|
uint32_t | wd_bitstream_ready_c1: 1 |
| |
|
uint32_t | bs_bitstream_valid_c1: 1 |
| |
|
uint32_t | bs_bitstream_ready_c1: 1 |
| |
|
uint32_t | reserved0: 8 |
| |
| } | |
| |
|
uint32_t | word |
| |
| }; | |
| |
|
union { |
|
struct { |
|
uint32_t | axi0_wr_limit_stall: 1 |
| |
|
uint32_t | axi1_ar_stalled: 1 |
| |
|
uint32_t | axi1_rd_limit_stall: 1 |
| |
|
uint32_t | axi1_wr_stalled: 1 |
| |
|
uint32_t | axi1_w_stalled: 1 |
| |
|
uint32_t | axi1_wr_limit_stall: 1 |
| |
|
uint32_t | wgt_idle_c1: 1 |
| |
|
uint32_t | bas_idle_c1: 1 |
| |
|
uint32_t | ib0_ai_valid_c1: 1 |
| |
|
uint32_t | ib0_ai_ready_c1: 1 |
| |
|
uint32_t | ib1_ai_valid_c1: 1 |
| |
|
uint32_t | ib1_ai_ready_c1: 1 |
| |
|
uint32_t | ib0_ao_valid_c1: 1 |
| |
|
uint32_t | ib0_ao_ready_c1: 1 |
| |
|
uint32_t | ib1_ao_valid_c1: 1 |
| |
|
uint32_t | ib1_ao_ready_c1: 1 |
| |
|
uint32_t | ob0_valid_c1: 1 |
| |
|
uint32_t | ob0_ready_c1: 1 |
| |
|
uint32_t | ob1_valid_c1: 1 |
| |
|
uint32_t | ob1_ready_c1: 1 |
| |
|
uint32_t | wd_bitstream_valid_c1: 1 |
| |
|
uint32_t | wd_bitstream_ready_c1: 1 |
| |
|
uint32_t | bs_bitstream_valid_c1: 1 |
| |
|
uint32_t | bs_bitstream_ready_c1: 1 |
| |
|
uint32_t | reserved0: 8 |
| |
| } | |
| |
|
uint32_t | word |
| |
| }; | |
| |
|
union { |
|
struct { |
|
uint32_t | axi_sram0_ar_stalled: 1 |
| |
|
uint32_t | axi_sram0_rd_limit_stall: 1 |
| |
|
uint32_t | axi_sram0_aw_stalled: 1 |
| |
|
uint32_t | axi_sram0_w_stalled: 1 |
| |
|
uint32_t | axi_sram0_wr_limit_stall: 1 |
| |
|
uint32_t | axi_sram1_ar_stalled: 1 |
| |
|
uint32_t | axi_sram1_rd_limit_stall: 1 |
| |
|
uint32_t | axi_sram1_aw_stalled: 1 |
| |
|
uint32_t | axi_sram1_w_stalled: 1 |
| |
|
uint32_t | axi_sram1_wr_limit_stall: 1 |
| |
|
uint32_t | axi_sram2_ar_stalled: 1 |
| |
|
uint32_t | axi_sram2_rd_limit_stall: 1 |
| |
|
uint32_t | axi_sram2_aw_stalled: 1 |
| |
|
uint32_t | axi_sram2_w_stalled: 1 |
| |
|
uint32_t | axi_sram2_wr_limit_stall: 1 |
| |
|
uint32_t | axi_sram3_ar_stalled: 1 |
| |
|
uint32_t | axi_sram3_rd_limit_stall: 1 |
| |
|
uint32_t | axi_sram3_aw_stalled: 1 |
| |
|
uint32_t | axi_sram3_w_stalled: 1 |
| |
|
uint32_t | axi_sram3_wr_limit_stall: 1 |
| |
|
uint32_t | axi_ext0_ar_stalled: 1 |
| |
|
uint32_t | axi_ext0_rd_limit_stall: 1 |
| |
|
uint32_t | axi_ext0_aw_stalled: 1 |
| |
|
uint32_t | axi_ext0_w_stalled: 1 |
| |
|
uint32_t | axi_ext0_wr_limit_stall: 1 |
| |
|
uint32_t | axi_ext1_ar_stalled: 1 |
| |
|
uint32_t | axi_ext1_rd_limit_stall: 1 |
| |
|
uint32_t | axi_ext1_aw_stalled: 1 |
| |
|
uint32_t | axi_ext1_w_stalled: 1 |
| |
|
uint32_t | axi_ext1_wr_limit_stall: 1 |
| |
|
uint32_t | reserved0: 2 |
| |
| } | |
| |
|
uint32_t | word |
| |
| }; | |
| |
