U55_Type Struct Reference

Description

Top level section for IP generation only, contains IP memory map (U55)

Data Fields
U55_BASE_1_0_Type	BASE_1_0
U55_BASE_POINTERS_1_0_Type	BASE_POINTERS_1_0
__IM uint32_t	RESERVED [16]
U55_PAGE_PMU_1_0_Type	PAGE_PMU_1_0
__IM uint32_t	RESERVED1 [640]
U55_PAGE_ID_1_0_Type	PAGE_ID_1_0
U55_MXU55_CTL_1_0_Type	MXU55_CTL_1_0
U55_MXU55_PPU_Type	MXU55_PPU
U55_PD_Type	PD

Field Documentation

BASE_1_0

U55_BASE_1_0_Type U55_Type::BASE_1_0

0x00000000 Page BASE

BASE_POINTERS_1_0

U55_BASE_POINTERS_1_0_Type U55_Type::BASE_POINTERS_1_0

0x00000080 Page BASE_POINTERS

RESERVED

__IM uint32_t U55_Type::RESERVED[16]

PAGE_PMU_1_0

U55_PAGE_PMU_1_0_Type U55_Type::PAGE_PMU_1_0

0x00000100 Page PMU

RESERVED1

__IM uint32_t U55_Type::RESERVED1[640]

PAGE_ID_1_0

U55_PAGE_ID_1_0_Type U55_Type::PAGE_ID_1_0

0x00000F00 Page ID and Component ID

MXU55_CTL_1_0

U55_MXU55_CTL_1_0_Type U55_Type::MXU55_CTL_1_0

0x00001000 System configuration settings

MXU55_PPU

U55_MXU55_PPU_Type U55_Type::MXU55_PPU

0x00002000 Power Policy Unit Registers for System RAM

PD

U55_PD_Type U55_Type::PD

0x00003000 Power Domain Controller