Description

Power Policy Unit Registers for System RAM (U55_MXU55_PPU)

Data Fields
__IOM uint32_t	PWPR

__IOM uint32_t	PMER

__IM uint32_t	PWSR

__IM uint32_t	RESERVED

__IM uint32_t	DISR

__IM uint32_t	MISR

__IM uint32_t	STSR

__IOM uint32_t	UNLK

__IOM uint32_t	PWCR

__IOM uint32_t	PTCR

__IM uint32_t	RESERVED1 [2]

__IOM uint32_t	IMR

__IOM uint32_t	AIMR

__IOM uint32_t	ISR

__IOM uint32_t	AISR

__IOM uint32_t	IESR

__IOM uint32_t	OPSR

__IM uint32_t	RESERVED2 [2]

__IOM uint32_t	FUNRR

__IOM uint32_t	FULRR

__IOM uint32_t	MEMRR

__IM uint32_t	RESERVED3 [65]

__IOM uint32_t	EDTR0

__IOM uint32_t	EDTR1

__IM uint32_t	RESERVED4 [2]

__IM uint32_t	DCDR0

__IM uint32_t	DCDR1

__IM uint32_t	RESERVED5 [910]

__IM uint32_t	IDR0

__IM uint32_t	IDR1

__IM uint32_t	RESERVED6 [4]

__IM uint32_t	IIDR

__IM uint32_t	AIDR

__IM uint32_t	PID4

__IM uint32_t	RESERVED7 [3]

__IM uint32_t	PID0

__IM uint32_t	PID1

__IM uint32_t	PID2

__IM uint32_t	PID3

__IM uint32_t	ID0

__IM uint32_t	ID1

__IM uint32_t	ID2

__IM uint32_t	ID3

Field Documentation

◆ PWPR

__IOM uint32_t U55_MXU55_PPU_Type::PWPR

0x00000000 Power Policy Register

◆ PMER

__IOM uint32_t U55_MXU55_PPU_Type::PMER

0x00000004 Power Mode Emulation Register

◆ PWSR

__IM uint32_t U55_MXU55_PPU_Type::PWSR

0x00000008 Power Status Register

◆ RESERVED

__IM uint32_t U55_MXU55_PPU_Type::RESERVED

◆ DISR

__IM uint32_t U55_MXU55_PPU_Type::DISR

0x00000010 Device Interface Input Current Status Register

◆ MISR

__IM uint32_t U55_MXU55_PPU_Type::MISR

0x00000014 Miscellaneous Input Current Status Register

◆ STSR

__IM uint32_t U55_MXU55_PPU_Type::STSR

0x00000018 Stored Status Register

◆ UNLK

__IOM uint32_t U55_MXU55_PPU_Type::UNLK

0x0000001C Unlock register

◆ PWCR

__IOM uint32_t U55_MXU55_PPU_Type::PWCR

0x00000020 Power Configuration Register

◆ PTCR

__IOM uint32_t U55_MXU55_PPU_Type::PTCR

0x00000024 Power Mode Transition Configuration Register

◆ RESERVED1

__IM uint32_t U55_MXU55_PPU_Type::RESERVED1[2]

◆ IMR

__IOM uint32_t U55_MXU55_PPU_Type::IMR

0x00000030 Interrupt Mask Register

◆ AIMR

__IOM uint32_t U55_MXU55_PPU_Type::AIMR

0x00000034 Additional Interrupt Mask Register

◆ ISR

__IOM uint32_t U55_MXU55_PPU_Type::ISR

0x00000038 Interrupt Status Register

◆ AISR

__IOM uint32_t U55_MXU55_PPU_Type::AISR

0x0000003C Additional Interrupt Status Register

◆ IESR

__IOM uint32_t U55_MXU55_PPU_Type::IESR

0x00000040 Input Edge Sensitivity Register

◆ OPSR

__IOM uint32_t U55_MXU55_PPU_Type::OPSR

0x00000044 Operating Mode Active Edge Sensitivity Register

◆ RESERVED2

__IM uint32_t U55_MXU55_PPU_Type::RESERVED2[2]

◆ FUNRR

__IOM uint32_t U55_MXU55_PPU_Type::FUNRR

0x00000050 Functional Retention RAM Configuration Register

◆ FULRR

__IOM uint32_t U55_MXU55_PPU_Type::FULRR

0x00000054 Full Retention RAM Configuration Register

◆ MEMRR

__IOM uint32_t U55_MXU55_PPU_Type::MEMRR

0x00000058 Memory Retention RAM Configuration Register

◆ RESERVED3

__IM uint32_t U55_MXU55_PPU_Type::RESERVED3[65]

◆ EDTR0

__IOM uint32_t U55_MXU55_PPU_Type::EDTR0

0x00000160 Power Mode Entry Delay Register 0

◆ EDTR1

__IOM uint32_t U55_MXU55_PPU_Type::EDTR1

0x00000164 Power Mode Entry Delay Register 1

◆ RESERVED4

__IM uint32_t U55_MXU55_PPU_Type::RESERVED4[2]

◆ DCDR0

__IM uint32_t U55_MXU55_PPU_Type::DCDR0

0x00000170 Device Control Delay Configuration Register 0

◆ DCDR1

__IM uint32_t U55_MXU55_PPU_Type::DCDR1

0x00000174 Device Control Delay Configuration Register 1

◆ RESERVED5

__IM uint32_t U55_MXU55_PPU_Type::RESERVED5[910]

◆ IDR0

__IM uint32_t U55_MXU55_PPU_Type::IDR0

0x00000FB0 PPU Identification Register 0

◆ IDR1

__IM uint32_t U55_MXU55_PPU_Type::IDR1

0x00000FB4 PPU Identification Register 1

◆ RESERVED6

__IM uint32_t U55_MXU55_PPU_Type::RESERVED6[4]

◆ IIDR

__IM uint32_t U55_MXU55_PPU_Type::IIDR

0x00000FC8 Implementation Identification Register

◆ AIDR

__IM uint32_t U55_MXU55_PPU_Type::AIDR

0x00000FCC Architecture Identification Register

◆ PID4

__IM uint32_t U55_MXU55_PPU_Type::PID4

0x00000FD0 Implementation Defined Identification Register (PID4)

◆ RESERVED7

__IM uint32_t U55_MXU55_PPU_Type::RESERVED7[3]

◆ PID0

__IM uint32_t U55_MXU55_PPU_Type::PID0

0x00000FE0 Implementation Defined Identification Register (PID0)

◆ PID1

__IM uint32_t U55_MXU55_PPU_Type::PID1

0x00000FE4 Implementation Defined Identification Register (PID1)

◆ PID2

__IM uint32_t U55_MXU55_PPU_Type::PID2

0x00000FE8 Implementation Defined Identification Register (PID2)

◆ PID3

__IM uint32_t U55_MXU55_PPU_Type::PID3

0x00000FEC Implementation Defined Identification Register (PID3)

◆ ID0

__IM uint32_t U55_MXU55_PPU_Type::ID0

0x00000FF0 Implementation Defined Identification Register (ID0)

◆ ID1

__IM uint32_t U55_MXU55_PPU_Type::ID1

0x00000FF4 Implementation Defined Identification Register (ID1)

◆ ID2

__IM uint32_t U55_MXU55_PPU_Type::ID2

0x00000FF8 Implementation Defined Identification Register (ID2)

◆ ID3

__IM uint32_t U55_MXU55_PPU_Type::ID3

0x00000FFC Implementation Defined Identification Register (ID3)