U55_BASE_1_0_Type Struct Reference

Description

Page BASE (U55_BASE_1_0)

Data Fields
__IM uint32_t	ID
__IM uint32_t	STATUS
__IOM uint32_t	CMD
__IOM uint32_t	RESET
__IOM uint32_t	QBASE0
__IOM uint32_t	QBASE1
__IM uint32_t	QREAD
__IOM uint32_t	QCONFIG
__IOM uint32_t	QSIZE
__IM uint32_t	PROT
__IM uint32_t	CONFIG
__IOM uint32_t	LOCK
__IM uint32_t	RESERVED [3]
__IOM uint32_t	REGIONCFG
__IOM uint32_t	AXI_LIMIT0
__IOM uint32_t	AXI_LIMIT1
__IOM uint32_t	AXI_LIMIT2
__IOM uint32_t	AXI_LIMIT3
__IM uint32_t	RESERVED1 [12]

Field Documentation

ID

__IM uint32_t U55_BASE_1_0_Type::ID

0x00000000 ID Register

STATUS

__IM uint32_t U55_BASE_1_0_Type::STATUS

0x00000004 Register describes the current operating status of the NPU

CMD

__IOM uint32_t U55_BASE_1_0_Type::CMD

0x00000008 Command register, reads as last written command

RESET

__IOM uint32_t U55_BASE_1_0_Type::RESET

0x0000000C Request Reset and new security mode

QBASE0

__IOM uint32_t U55_BASE_1_0_Type::QBASE0

0x00000010 Base address of Command-queue bits [31 downto 0]. The address is 4-byte-aligned

QBASE1

__IOM uint32_t U55_BASE_1_0_Type::QBASE1

0x00000014 Address extension bits [47 downto 32] for queue base

QREAD

__IM uint32_t U55_BASE_1_0_Type::QREAD

0x00000018 Read offset in the command stream in bytes. Multiples of 4 in the range 0-16 MB

QCONFIG

__IOM uint32_t U55_BASE_1_0_Type::QCONFIG

0x0000001C AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG

QSIZE

__IOM uint32_t U55_BASE_1_0_Type::QSIZE

0x00000020 Size of the command stream in bytes. Multiples of 4 in the range 0-16 MB

PROT

__IM uint32_t U55_BASE_1_0_Type::PROT

0x00000024 Protection level configured for the NPU when acting as an AXI master

CONFIG

__IM uint32_t U55_BASE_1_0_Type::CONFIG

0x00000028 RTL configuration

LOCK

__IOM uint32_t U55_BASE_1_0_Type::LOCK

0x0000002C Lock register. This register is designed for driver use and does not affect NPU functionality

RESERVED

__IM uint32_t U55_BASE_1_0_Type::RESERVED[3]

REGIONCFG

__IOM uint32_t U55_BASE_1_0_Type::REGIONCFG

0x0000003C Base pointer configuration. Bits[2*k+1 downto 2*k] give the memory type for REGION[k]

AXI_LIMIT0

__IOM uint32_t U55_BASE_1_0_Type::AXI_LIMIT0

0x00000040 AXI limits for port 0 counter 0

AXI_LIMIT1

__IOM uint32_t U55_BASE_1_0_Type::AXI_LIMIT1

0x00000044 AXI limits for port 0 counter 1

AXI_LIMIT2

__IOM uint32_t U55_BASE_1_0_Type::AXI_LIMIT2

0x00000048 AXI limits for port 1 counter 2

AXI_LIMIT3

__IOM uint32_t U55_BASE_1_0_Type::AXI_LIMIT3

0x0000004C AXI limits for port 1 counter 3

RESERVED1

__IM uint32_t U55_BASE_1_0_Type::RESERVED1[12]