Description

Serial Memory Interface (SMIF_CORE)

Data Fields
__IOM uint32_t	CTL

__IM uint32_t	STATUS

__IOM uint32_t	CTL2

__IM uint32_t	RESERVED

__IM uint32_t	DLP_DELAY_TAP_SEL0

__IM uint32_t	DLP_DELAY_TAP_SEL1

__IOM uint32_t	DLP_CTL

__IM uint32_t	RESERVED1

__IM uint32_t	DLP_STATUS0

__IM uint32_t	DLP_STATUS1

__IM uint32_t	RESERVED2 [7]

__IM uint32_t	TX_CMD_FIFO_STATUS

__IM uint32_t	TX_CMD_MMIO_FIFO_STATUS

__IM uint32_t	RESERVED3

__OM uint32_t	TX_CMD_MMIO_FIFO_WR

__IM uint32_t	RESERVED4 [11]

__IOM uint32_t	TX_DATA_MMIO_FIFO_CTL

__IM uint32_t	TX_DATA_FIFO_STATUS

__IM uint32_t	TX_DATA_MMIO_FIFO_STATUS

__IM uint32_t	RESERVED5

__OM uint32_t	TX_DATA_MMIO_FIFO_WR1

__OM uint32_t	TX_DATA_MMIO_FIFO_WR2

__OM uint32_t	TX_DATA_MMIO_FIFO_WR4

__OM uint32_t	TX_DATA_MMIO_FIFO_WR1ODD

__IM uint32_t	RESERVED6 [8]

__IOM uint32_t	RX_DATA_MMIO_FIFO_CTL

__IM uint32_t	RX_DATA_MMIO_FIFO_STATUS

__IM uint32_t	RX_DATA_FIFO_STATUS

__IM uint32_t	RESERVED7

__IM uint32_t	RX_DATA_MMIO_FIFO_RD1

__IM uint32_t	RX_DATA_MMIO_FIFO_RD2

__IM uint32_t	RX_DATA_MMIO_FIFO_RD4

__IM uint32_t	RESERVED8

__IM uint32_t	RX_DATA_MMIO_FIFO_RD1_SILENT

__IM uint32_t	RESERVED9 [7]

__IOM uint32_t	SLOW_CA_CTL

__IM uint32_t	RESERVED10

__IOM uint32_t	SLOW_CA_CMD

__IM uint32_t	RESERVED11 [29]

__IOM uint32_t	FAST_CA_CTL

__IM uint32_t	RESERVED12

__IOM uint32_t	FAST_CA_CMD

__IM uint32_t	RESERVED13 [29]

SMIF_CORE_SMIF_CRYPTO_Type	SMIF_CRYPTO_BLOCK [4]

__IM uint32_t	RESERVED14 [128]

__IOM uint32_t	CRC_CMD

__IM uint32_t	RESERVED15 [7]

__IOM uint32_t	CRC_INPUT0

__IOM uint32_t	CRC_INPUT1

__IM uint32_t	RESERVED16 [6]

__IM uint32_t	CRC_OUTPUT

__IM uint32_t	RESERVED17 [95]

__IOM uint32_t	INTR

__IOM uint32_t	INTR_SET

__IOM uint32_t	INTR_MASK

__IM uint32_t	INTR_MASKED

__IM uint32_t	RESERVED18 [2]

__IOM uint32_t	DLL_IDAC

__IOM uint32_t	DLL_IVR

__IM uint32_t	RESERVED19 [8]

SMIF_CORE_DEVICE_Type	DEVICE [4]

__IM uint32_t	RESERVED20 [2432]

SMIF_CORE_AXI_Type	AXI

SMIF_CORE_SMIF_HSIOM_Type	SMIF_HSIOM

__IM uint32_t	RESERVED21 [8192]

SMIF_CORE_SMIF_GPIO_Type	SMIF_GPIO

Field Documentation

◆ CTL

__IOM uint32_t SMIF_CORE_Type::CTL

0x00000000 Control

◆ STATUS

__IM uint32_t SMIF_CORE_Type::STATUS

0x00000004 Status

◆ CTL2

__IOM uint32_t SMIF_CORE_Type::CTL2

0x00000008 Control 2

◆ RESERVED

__IM uint32_t SMIF_CORE_Type::RESERVED

◆ DLP_DELAY_TAP_SEL0

__IM uint32_t SMIF_CORE_Type::DLP_DELAY_TAP_SEL0

0x00000010 DLP Delay Tap Select Register 0

◆ DLP_DELAY_TAP_SEL1

__IM uint32_t SMIF_CORE_Type::DLP_DELAY_TAP_SEL1

0x00000014 DLP Delay Tap Select Register 1

◆ DLP_CTL

__IOM uint32_t SMIF_CORE_Type::DLP_CTL

0x00000018 DLP Control Register

◆ RESERVED1

__IM uint32_t SMIF_CORE_Type::RESERVED1

◆ DLP_STATUS0

__IM uint32_t SMIF_CORE_Type::DLP_STATUS0

0x00000020 DLP Status Register 0

◆ DLP_STATUS1

__IM uint32_t SMIF_CORE_Type::DLP_STATUS1

0x00000024 DLP Status Register 1

◆ RESERVED2

__IM uint32_t SMIF_CORE_Type::RESERVED2[7]

◆ TX_CMD_FIFO_STATUS

__IM uint32_t SMIF_CORE_Type::TX_CMD_FIFO_STATUS

0x00000044 Transmitter command FIFO status

◆ TX_CMD_MMIO_FIFO_STATUS

__IM uint32_t SMIF_CORE_Type::TX_CMD_MMIO_FIFO_STATUS

0x00000048 Transmitter command MMIO FIFO status

◆ RESERVED3

__IM uint32_t SMIF_CORE_Type::RESERVED3

◆ TX_CMD_MMIO_FIFO_WR

__OM uint32_t SMIF_CORE_Type::TX_CMD_MMIO_FIFO_WR

0x00000050 Transmitter command MMIO FIFO write

◆ RESERVED4

__IM uint32_t SMIF_CORE_Type::RESERVED4[11]

◆ TX_DATA_MMIO_FIFO_CTL

__IOM uint32_t SMIF_CORE_Type::TX_DATA_MMIO_FIFO_CTL

0x00000080 Transmitter data MMIO FIFO control

◆ TX_DATA_FIFO_STATUS

__IM uint32_t SMIF_CORE_Type::TX_DATA_FIFO_STATUS

0x00000084 Transmitter data FIFO status

◆ TX_DATA_MMIO_FIFO_STATUS

__IM uint32_t SMIF_CORE_Type::TX_DATA_MMIO_FIFO_STATUS

0x00000088 Transmitter data MMIO FIFO status

◆ RESERVED5

__IM uint32_t SMIF_CORE_Type::RESERVED5

◆ TX_DATA_MMIO_FIFO_WR1

__OM uint32_t SMIF_CORE_Type::TX_DATA_MMIO_FIFO_WR1

0x00000090 Transmitter data MMIO FIFO write

◆ TX_DATA_MMIO_FIFO_WR2

__OM uint32_t SMIF_CORE_Type::TX_DATA_MMIO_FIFO_WR2

0x00000094 Transmitter data MMIO FIFO write

◆ TX_DATA_MMIO_FIFO_WR4

__OM uint32_t SMIF_CORE_Type::TX_DATA_MMIO_FIFO_WR4

0x00000098 Transmitter data MMIO FIFO write

◆ TX_DATA_MMIO_FIFO_WR1ODD

__OM uint32_t SMIF_CORE_Type::TX_DATA_MMIO_FIFO_WR1ODD

0x0000009C Transmitter data MMIO FIFO write

◆ RESERVED6

__IM uint32_t SMIF_CORE_Type::RESERVED6[8]

◆ RX_DATA_MMIO_FIFO_CTL

__IOM uint32_t SMIF_CORE_Type::RX_DATA_MMIO_FIFO_CTL

0x000000C0 Receiver data MMIO FIFO control

◆ RX_DATA_MMIO_FIFO_STATUS

__IM uint32_t SMIF_CORE_Type::RX_DATA_MMIO_FIFO_STATUS

0x000000C4 Receiver data MMIO FIFO status

◆ RX_DATA_FIFO_STATUS

__IM uint32_t SMIF_CORE_Type::RX_DATA_FIFO_STATUS

0x000000C8 Receiver data FIFO status

◆ RESERVED7

__IM uint32_t SMIF_CORE_Type::RESERVED7

◆ RX_DATA_MMIO_FIFO_RD1

__IM uint32_t SMIF_CORE_Type::RX_DATA_MMIO_FIFO_RD1

0x000000D0 Receiver data MMIO FIFO read

◆ RX_DATA_MMIO_FIFO_RD2

__IM uint32_t SMIF_CORE_Type::RX_DATA_MMIO_FIFO_RD2

0x000000D4 Receiver data MMIO FIFO read

◆ RX_DATA_MMIO_FIFO_RD4

__IM uint32_t SMIF_CORE_Type::RX_DATA_MMIO_FIFO_RD4

0x000000D8 Receiver data MMIO FIFO read

◆ RESERVED8

__IM uint32_t SMIF_CORE_Type::RESERVED8

◆ RX_DATA_MMIO_FIFO_RD1_SILENT

__IM uint32_t SMIF_CORE_Type::RX_DATA_MMIO_FIFO_RD1_SILENT

0x000000E0 Receiver data MMIO FIFO silent read

◆ RESERVED9

__IM uint32_t SMIF_CORE_Type::RESERVED9[7]

◆ SLOW_CA_CTL

__IOM uint32_t SMIF_CORE_Type::SLOW_CA_CTL

0x00000100 Slow cache control

◆ RESERVED10

__IM uint32_t SMIF_CORE_Type::RESERVED10

◆ SLOW_CA_CMD

__IOM uint32_t SMIF_CORE_Type::SLOW_CA_CMD

0x00000108 Slow cache command

◆ RESERVED11

__IM uint32_t SMIF_CORE_Type::RESERVED11[29]

◆ FAST_CA_CTL

__IOM uint32_t SMIF_CORE_Type::FAST_CA_CTL

0x00000180 Fast cache control

◆ RESERVED12

__IM uint32_t SMIF_CORE_Type::RESERVED12

◆ FAST_CA_CMD

__IOM uint32_t SMIF_CORE_Type::FAST_CA_CMD

0x00000188 Fast cache command

◆ RESERVED13

__IM uint32_t SMIF_CORE_Type::RESERVED13[29]

◆ SMIF_CRYPTO_BLOCK

SMIF_CORE_SMIF_CRYPTO_Type SMIF_CORE_Type::SMIF_CRYPTO_BLOCK[4]

0x00000200 Cryptography registers (one set for each key)

◆ RESERVED14

__IM uint32_t SMIF_CORE_Type::RESERVED14[128]

◆ CRC_CMD

__IOM uint32_t SMIF_CORE_Type::CRC_CMD

0x00000600 CRC Command

◆ RESERVED15

__IM uint32_t SMIF_CORE_Type::RESERVED15[7]

◆ CRC_INPUT0

__IOM uint32_t SMIF_CORE_Type::CRC_INPUT0

0x00000620 CRC input 0

◆ CRC_INPUT1

__IOM uint32_t SMIF_CORE_Type::CRC_INPUT1

0x00000624 CRC input 1

◆ RESERVED16

__IM uint32_t SMIF_CORE_Type::RESERVED16[6]

◆ CRC_OUTPUT

__IM uint32_t SMIF_CORE_Type::CRC_OUTPUT

0x00000640 CRC output

◆ RESERVED17

__IM uint32_t SMIF_CORE_Type::RESERVED17[95]

◆ INTR

__IOM uint32_t SMIF_CORE_Type::INTR

0x000007C0 Interrupt register

◆ INTR_SET

__IOM uint32_t SMIF_CORE_Type::INTR_SET

0x000007C4 Interrupt set register

◆ INTR_MASK

__IOM uint32_t SMIF_CORE_Type::INTR_MASK

0x000007C8 Interrupt mask register

◆ INTR_MASKED

__IM uint32_t SMIF_CORE_Type::INTR_MASKED

0x000007CC Interrupt masked register

◆ RESERVED18

__IM uint32_t SMIF_CORE_Type::RESERVED18[2]

◆ DLL_IDAC

__IOM uint32_t SMIF_CORE_Type::DLL_IDAC

0x000007D8 DLL IDAC ( when DLL runs in open loop, selects the delay of the delay line)

◆ DLL_IVR

__IOM uint32_t SMIF_CORE_Type::DLL_IVR

0x000007DC DLL IVR (Contol Output Voltage of internal Voltage Regulator )

◆ RESERVED19

__IM uint32_t SMIF_CORE_Type::RESERVED19[8]

◆ DEVICE

SMIF_CORE_DEVICE_Type SMIF_CORE_Type::DEVICE[4]

0x00000800 Device (only used for XIP acceses)

◆ RESERVED20

__IM uint32_t SMIF_CORE_Type::RESERVED20[2432]

◆ AXI

SMIF_CORE_AXI_Type SMIF_CORE_Type::AXI

0x00003000 Serial Memory Interface

◆ SMIF_HSIOM

SMIF_CORE_SMIF_HSIOM_Type SMIF_CORE_Type::SMIF_HSIOM

0x00004000 IO Matrix (IOM)

◆ RESERVED21

__IM uint32_t SMIF_CORE_Type::RESERVED21[8192]

◆ SMIF_GPIO

SMIF_CORE_SMIF_GPIO_Type SMIF_CORE_Type::SMIF_GPIO

0x00010000 IO port control/configuration