Description

AXI DMA controller channel (SAXI_DMAC_CH)

Data Fields
__IOM uint32_t	CTL

__IM uint32_t	STATUS

__IM uint32_t	RESERVED [2]

__IM uint32_t	IDX

__IM uint32_t	SRC

__IM uint32_t	DST

__IM uint32_t	M_IDX

__IOM uint32_t	CURR

__IM uint32_t	RESERVED1

__IOM uint32_t	TR_CMD

__IM uint32_t	RESERVED2 [5]

__IM uint32_t	DESCR_STATUS

__IM uint32_t	RESERVED3 [3]

__IM uint32_t	DESCR_CTL

__IM uint32_t	DESCR_SRC

__IM uint32_t	DESCR_DST

__IM uint32_t	DESCR_M_SIZE

__IM uint32_t	DESCR_X_SIZE

__IM uint32_t	DESCR_X_INCR

__IM uint32_t	DESCR_Y_SIZE

__IM uint32_t	DESCR_Y_INCR

__IM uint32_t	DESCR_NEXT

__IM uint32_t	RESERVED4 [3]

__IOM uint32_t	INTR

__IOM uint32_t	INTR_SET

__IOM uint32_t	INTR_MASK

__IM uint32_t	INTR_MASKED

__IM uint32_t	RESERVED5 [28]

Field Documentation

◆ CTL

__IOM uint32_t SAXI_DMAC_CH_Type::CTL

0x00000000 Channel control

◆ STATUS

__IM uint32_t SAXI_DMAC_CH_Type::STATUS

0x00000004 Channel status

◆ RESERVED

__IM uint32_t SAXI_DMAC_CH_Type::RESERVED[2]

◆ IDX

__IM uint32_t SAXI_DMAC_CH_Type::IDX

0x00000010 Channel current X and Y indices

◆ SRC

__IM uint32_t SAXI_DMAC_CH_Type::SRC

0x00000014 Channel current source address

◆ DST

__IM uint32_t SAXI_DMAC_CH_Type::DST

0x00000018 Channel current destination address

◆ M_IDX

__IM uint32_t SAXI_DMAC_CH_Type::M_IDX

0x0000001C Channel current M index

◆ CURR

__IOM uint32_t SAXI_DMAC_CH_Type::CURR

0x00000020 Channel current descriptor pointer

◆ RESERVED1

__IM uint32_t SAXI_DMAC_CH_Type::RESERVED1

◆ TR_CMD

__IOM uint32_t SAXI_DMAC_CH_Type::TR_CMD

0x00000028 Channel software trigger

◆ RESERVED2

__IM uint32_t SAXI_DMAC_CH_Type::RESERVED2[5]

◆ DESCR_STATUS

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_STATUS

0x00000040 Channel descriptor status

◆ RESERVED3

__IM uint32_t SAXI_DMAC_CH_Type::RESERVED3[3]

◆ DESCR_CTL

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_CTL

0x00000050 Channel descriptor control

◆ DESCR_SRC

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_SRC

0x00000054 Channel descriptor source

◆ DESCR_DST

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_DST

0x00000058 Channel descriptor destination

◆ DESCR_M_SIZE

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_M_SIZE

0x0000005C Channel descriptor M size

◆ DESCR_X_SIZE

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_X_SIZE

0x00000060 Channel descriptor X size

◆ DESCR_X_INCR

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_X_INCR

0x00000064 Channel descriptor X increment

◆ DESCR_Y_SIZE

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_Y_SIZE

0x00000068 Channel descriptor Y size

◆ DESCR_Y_INCR

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_Y_INCR

0x0000006C Channel descriptor Y increment

◆ DESCR_NEXT

__IM uint32_t SAXI_DMAC_CH_Type::DESCR_NEXT

0x00000070 Channel descriptor next pointer

◆ RESERVED4

__IM uint32_t SAXI_DMAC_CH_Type::RESERVED4[3]

◆ INTR

__IOM uint32_t SAXI_DMAC_CH_Type::INTR

0x00000080 Interrupt

◆ INTR_SET

__IOM uint32_t SAXI_DMAC_CH_Type::INTR_SET

0x00000084 Interrupt set

◆ INTR_MASK

__IOM uint32_t SAXI_DMAC_CH_Type::INTR_MASK

0x00000088 Interrupt mask

◆ INTR_MASKED

__IM uint32_t SAXI_DMAC_CH_Type::INTR_MASKED

0x0000008C Interrupt masked

◆ RESERVED5

__IM uint32_t SAXI_DMAC_CH_Type::RESERVED5[28]