RAMC0/1/2 (RAMC)
Data Fields | |
| __IOM uint32_t | CTL |
| __IM uint32_t | RESERVED |
| __IM uint32_t | STATUS |
| __IM uint32_t | RESERVED1 [5] |
| __IOM uint32_t | ECC_CTL |
| __IM uint32_t | ECC_STATUS0 |
| __IM uint32_t | ECC_STATUS1 |
| __IM uint32_t | RESERVED2 [54] |
| __IOM uint32_t | ECC_MATCH |
| __IM uint32_t | RESERVED3 [62] |
| __IOM uint32_t | PWR_MACRO_CTL |
| __IM uint32_t | RESERVED4 [15] |
| __IOM uint32_t | PWR_MACRO_CTL_LOCK |
| __IM uint32_t | RESERVED5 [15] |
| __IOM uint32_t | PWR_DELAY_CTL |
| __IM uint32_t | RESERVED6 [3935] |
| RAMC_MPC_Type | MPC [1] |
| __IOM uint32_t RAMC_Type::CTL |
0x00000000 Control
| __IM uint32_t RAMC_Type::RESERVED |
| __IM uint32_t RAMC_Type::STATUS |
0x00000008 Status
| __IM uint32_t RAMC_Type::RESERVED1[5] |
| __IOM uint32_t RAMC_Type::ECC_CTL |
0x00000020 ECC control
| __IM uint32_t RAMC_Type::ECC_STATUS0 |
0x00000024 ECC status 0
| __IM uint32_t RAMC_Type::ECC_STATUS1 |
0x00000028 ECC status 1
| __IM uint32_t RAMC_Type::RESERVED2[54] |
| __IOM uint32_t RAMC_Type::ECC_MATCH |
0x00000104 ECC match
| __IM uint32_t RAMC_Type::RESERVED3[62] |
| __IOM uint32_t RAMC_Type::PWR_MACRO_CTL |
0x00000200 SRAM power partition power control
| __IM uint32_t RAMC_Type::RESERVED4[15] |
| __IOM uint32_t RAMC_Type::PWR_MACRO_CTL_LOCK |
0x00000240 SRAM power partition power control Lock
| __IM uint32_t RAMC_Type::RESERVED5[15] |
| __IOM uint32_t RAMC_Type::PWR_DELAY_CTL |
0x00000280 SRAM power switch power up & sequence delay
| __IM uint32_t RAMC_Type::RESERVED6[3935] |
| RAMC_MPC_Type RAMC_Type::MPC[1] |
0x00004000 MPC Memory Protection Controller registers